NOVA
-16
Enhanced ISA Emulator · 16-bit · Cache · Hazard Detection · Branch Prediction
—
CPI
0
CYCLES
—
CACHE HIT%
—
BR.PRED%
16 regs
19 opcodes
L1 cache
● IDLE
⌨ assembly editor
— examples —
Add numbers
Countdown loop
Fibonacci
Bubble sort (2 elements)
Subroutine CALL/RET
Data hazard demo
Bitwise ops demo
1
✦ AI code generator
Gemini 2.0 Flash
▼
sum 1–10
factorial 5
sort 3 vals
CALL/RET demo
hazard demo
GCD
✦ generate
(Ctrl+Enter)
generated code
insert into editor ↑
IF · Fetch
—
ID · Decode
—
EX · Execute
—
MEM · Access
—
WB · Writeback
—
hazards
data: none
ctrl: none
struct: none
stalls: 0 · forwards: 0 · mispredicts: 0
registers (R0–R15)
L1 data cache (8-line direct-mapped)
hits:
0
misses:
0
rate:
—
memory — 256 words
execution trace
cpu state
PC
0x00
SP (stack ptr)
0xFF
IR
0x0000
cycles
0
instructions
0
CPI
—
Z
N
C
V
HALT
CPI breakdown
ALU
0
MEM
0
BRANCH
0
STALL
0
branch predictor (2-bit saturating)
predictions
0
correct
0
mispredicts
0
accuracy
—
2-bit counter state:
0
0
0
0
instruction reference